GCC Compiler Engineer

Tenstorrent|13 Feb 2024

fulltimeonsite

Job Description

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

We are seeking a GCC Compiler Engineer to design, develop, and optimize compilers for next-generation RISC-V and AI compute architectures. You will work across hardware and software teams to improve performance, programmability, and integration of our custom toolchains into real applications. This role is fully hands-on and central to how developers interact with Tenstorrent hardware across both traditional compute and advanced machine learning workloads.

This role is Hybrid, based out of Santa Clara, CA, Austin, TX, or Toronto, ON.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

Experienced compiler engineer with deep knowledge of GCC and LLVM internals, comfortable optimizing for custom hardware targets.
Strong C/C++ developer with a solid grasp of algorithms, data structures, and performance analysis.
Collaborative and analytical, able to work across hardware and software domains to deliver efficient, high-performance toolchains.
Passionate about enabling breakthrough compute architectures through compiler innovation and software-hardware co-design.

What We Need

Design, develop, and optimize GCC and/or LLVM compilers for Tenstorrent’s custom RISC-V hardware and AI vector engines.
Contribute to the co-design of Tenstorrent’s hardware and software stack to maximize performance and programmability.
Benchmark, analyze, and tune performance of core applications across RISC-V and AI software environments.
Collaborate with ML engineers to identify and implement compiler support for emerging AI workloads and frameworks.

What You’ll Learn

How compiler design directly impacts the performance and efficiency of next-generation RISC-V and AI architectures.
Advanced techniques in hardware-software co-optimization and compiler-driven performance tuning.
Integration of custom compilers with leading ML frameworks and runtime environments.
The end-to-end toolchain flow that enables Tenstorrent’s scalable, high-performance AI compute systems.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.