Before you apply
Listed location: China, Shanghai
Work arrangement: onsite. A remote label does not confirm worldwide eligibility or visa sponsorship.
Read the employer’s description for qualifications, compensation and work eligibility. Confirm the position is still open on the application page.
Job description supplied by NVIDIA; category and skill labels may be inferred. How our listings work · Report a problem
Job Description
The NVIDIA GPU clocks group is looking for an excellent Senior ASIC Design Engineer to join the team. The Team is responsible for crafting all aspects of GPU clocking. We collaborate with the frontend design team to understand the clocking requirements for the chip, and work with backend teams to understand the physical restrictions. The GPU clocks group architects, designs and validates the clocks RTL. The complexity of clocks RTL has increased many fold to support our features that power our product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.
What you’ll be doing:
As a Clocks team member, you will collaborate with other architects, ASIC designers and verification engineers to design high frequency and low power clocks. You should be able to engage with multiple teams and design the GPU clocks to satisfy all the architectural constraints. You will need to run and enhance some in-house flow to guarantee the good quality of clocks RTL and netlist, drive the issues to close. Together with other team members, we deliver clock information to SOC verification team, timing and DFT teams. You will use Perl/Python to improve the productivity of the above teams. Collaborate with software and silicon solution team to debug GPU clock silicon bugs in our new products.
What we need to see:
BS or (MS preferred) in EE or equivalent experience. 2+ years of meaningful work experience.
Your ability to thrive in a dynamically changing environment.
Validated experience in RTL design (Verilog), verification and logic synthesis. Your strong coding skills in Perl or Python or other industry-standard scripting languages.
Deep understanding of sub-micron silicon issues like noise, cross-talk, and OCV effects is a plus. Good understanding of backend flows and requirements is a plus.
DFT knowledge is a plus. Experience in implementing on-chip clocking networks is desirable.
Excellent analytical and problem-solving skills. Fluent English (both written and spoken) and excellent communication skills.
Good team work spirit, easy to cooperate with team members.
Skills mentioned
Categories
Frequently asked questions
Is the ASIC Design Engineer, Clocks position at NVIDIA remote?
The ASIC Design Engineer, Clocks role at NVIDIA does not have a confirmed remote arrangement in our data. Check the employer description for its work location.
What type of employment is the ASIC Design Engineer, Clocks role?
NVIDIA is hiring for a full-time ASIC Design Engineer, Clocks position.
Which skills are mentioned for the ASIC Design Engineer, Clocks job at NVIDIA?
Detected skill labels include Python, GPU. Check the employer description to distinguish required skills from preferred experience.
How do I apply for the ASIC Design Engineer, Clocks position at NVIDIA?
You can apply for the ASIC Design Engineer, Clocks role directly through NVIDIA's official application link provided on this page.
Similar AI jobs
Director, Real Estate Development
NVIDIA · fulltime
Software Engineer, New Grad (2027)
Harvey · fulltime
Software Engineer, New Grad (2027)
Harvey · fulltime
Vice President, Product Management, Managed AI
Crusoe · fulltime
Senior Software Engineer — Backend (Files Team)
Databricks · fulltime
Senior Detection and Response Engineer
Anyscale · fulltime