Staff Electrical Engineer - Aggregator

JOB SUMMARY

We're looking for a Staff Electrical Engineer to architect the electronics for Apollo’s sensor bridge. Strong candidates will have experience with FPGA hardware for both PCBA design and RTL development. This role works closely with the perception team to give Apollo sight and enable critical safety functions. This role owns the full electrical and FPGA stack of one board, end to end: requirements, architecture, schematic capture, layout guidance, RTL, bring-up, validation, and the transition to production.

ESSENTIAL DUTIES AND RESPONSIBILITIES or KEY ACCOUNTABILITIES

• Electronics & FPGA Architect from Concept to Production: Own requirements definition, part selection, schematic capture, layout guidance, and RTL architecture for a multi-Gbps, mixed-signal PCBA that aggregates camera sensor data and human-robot interface functions into an efficient cable interface routed across dynamic joints. Carry the design from architecture through prototype, validation, and manufacturing release. Generate and maintain design documentation: block diagrams, schematics, RTL architecture docs, test plans, and fab/assembly drawings.
• High-Speed & Mixed-Signal Hardware Design: Design and validate high-speed digital interfaces (CSI-2, GMSL2/FPD-Link/PoC, 10GbE) including signal integrity, impedance control, and length-matching. Architect the board's power tree for proper power sequencing and low-power consumption. Design for EMC, ESD, and thermal constraints.
• FPGA Device Selection, Architecture, and RTL Development: Define FPGA device selection and architecture for the sensor bridge node(s). Develop RTL (VHDL/Verilog) for CSI-2 ingest, Ethernet packetization, timestamp/metadata insertion, and camera synchronization for deterministic multi-camera and multi-IMU synchronization. Own timing closure, clock-domain crossing, and resource/power budgeting within the FPGA. Select and integrate high-speed transceivers and external PHYs.
• Validation, Bring-Up, and Debugging: Develop and execute validation plans spanning board-level and FPGA-level testing. Build test fixtures and use lab equipment (high-bandwidth oscilloscopes, protocol analyzers, logic analyzers) to validate latency, bandwidth, and synchronization requirements. Debug across the hardware/RTL boundary — link training failures, timing violations, ISP misconfiguration, power sequencing faults — using rigorous, first-principles root-cause analysis.
• Lifecycle Management & Vendor Alignment: Own the entire component lifecycle through PLM systems, managing third-party relationships with hardware vendors and contract manufacturers (CMs) to ensure successful production scaling and design-for-manufacturability (DFM/DFA).
• Cross-Functional Collaboration: Collaborate closely with cross-functional teams, including technical lead, project managers, software, mechanical, thermal, systems engineers, and manufacturing. Act as a mentor within the electrical engineering team, guiding junior engineers on best practices for hardware design, documentation, and troubleshooting.
• Technical Leadership: Drive project execution with leadership, program management, and engineering peers. Define component roadmaps with product managers, systems engineers, and technical leads. Lead debugging and root cause analysis related to hardware and software defect resolution. Align technical implementation and execution with company goals. Drive consensus with stakeholders on critical design and compliance decisions. Provide work breakdowns and time estimations to inform project execution.

SKILLS AND REQUIREMENTS

• Strong, demonstrated depth in FPGA hardware design for time-sensitive, high-performance applications (image processing, high-speed data acquisition, real-time networking, or similar), including:
• FPGA device selection and architecture definition
• RTL development in VHDL and/or Verilog
• High-speed interface design (CSI-2, GMSL/SerDes, Ethernet, PCIe, or comparable)
• Timing closure, clock-domain crossing, and resource optimization
• Integration of high-speed transceivers and external PHY devices
• FPGA tool flows (Vivado, Quartus, or Lattice Radiant) and simulation (ModelSim/Questa or equivalent)
• Deep understanding of high-speed digital design fundamentals: signal integrity, impedance-controlled routing, differential pairs, stack-up, and timing analysis across the board-to-FPGA boundary.
• Experience with camera/image sensor hardware: SerDes (GMSL, FPD-Link, or similar), MIPI CSI-2, and ISP integration — automotive or robotics vision systems strongly preferred.
• Experience with Ethernet-based sensor streaming and sensor bridges.
• Excellent communication (verbal & written); will be expected to develop detailed build assembly instructions and diagrams.
• Excellent problem-solving and hardware debugging skills. Hands-on experience with prototyping and testing, including the use of lab equipment.
• Drive Through Influence: Exceptional ability to lead technical initiatives and align cross-functional stakeholders without direct reporting authority, using empirical data from the lab to drive decisions.
• Ability to thrive in a fast-paced, high-growth environment where "perfect" is the enemy of "shipped," knowing exactly when a design is robust enough for the real world.
• Travel up to 10% within US and internationally.

EDUCATION and/or EXPERIENCE

• Bachelors, Masters, or PhD degree in Electrical Engineering or related field.
• At least 8 years of experience in Electrical Engineering.

PHYSICAL REQUIREMENTS 

• Prolonged periods of sitting at a desk and working on a computer
• Must be able to lift 15 pounds at times
• Vision to read printed materials and a computer screen
• Hearing and speech to communicate