RTL Power Optimization Engineer – New College Grad 2026

Our team is privileged to work on Power Optimization of Data center, gaming and automotive GPU chips. We also work on power optimization of Networking chips. The gamut of GPUs and networking chips requires the team to provide architecture, micro-architecture, RTL Design, methodology and AI based power optimization solutions. You will collaborate with Architects, Performance Engineers, Software Engineers, ASIC Design Engineers, and Physical Design teams to study and implement power analysis and reduction techniques for NVIDIA's next generation GPUs and Networking products. Your contributions will help us gain early insight into energy consumption of graphics and artificial intelligence workloads, and will allow us to influence architectural, design, and power management improvements.

What You'll Be Doing:

• Use internally developed tools and industry standard pre-silicon gate-level and RTL power analysis tools, to help improve product power efficiency.

• Use artificial intelligence to devliver RTL and/or Architecture Power optimization solutions.

• Develop and share best practices for performing pre-silicon power analysis.

• Perform comparative power analysis, to spot trends and anomalies, that warrant more scrutiny.

• Interact with architects and RTL designers to help them interpret their power data and identify power bugs; drive them to implement fixes.

• Select and run a wide variety of workloads for power analysis.

• Prototype a new architectural feature in Verilog and analyze power.

What We Need To See:

• Pursuing or recently completed a MS or PhD in Electrical Engineering, Computer Engineering, or related fields with coursework or experience in AI, Digital Design and VLSI concepts (or equivalent experience).

• Understanding of RTL power optimization fundamentals, including switching activity, clock/enable efficiency, and common low‑power design patterns at the RTL level.

• Knowledge of backend flows such as logic synthesis and place‑and‑route, and how RTL decisions impact post‑layout power and timing.

• Familiarity with RTL implementation of low‑power techniques (e.g., clock gating, operand isolation, power gating strategies, multi‑VT usage) and their trade‑offs.

• Exposure to industry power analysis tools such as PowerArtist, PrimeTime PX, or equivalent, including running power analysis and interpreting reports to guide design changes.

• Strong Python programming skills for building automation scripts, data pipelines, and AI/ML‑driven analysis flows for RTL power optimization.

• Coursework and/or hands‑on experience in Machine Learning and Artificial Intelligence, with ability to apply ML techniques to EDA and silicon power problems.

• Previous experience debugging RTL or gate‑level power anomalies by tracing logic cones, examining activity/toggle data, and identifying root‑cause structures or scenarios.

• Strong written and verbal communication skills to document methodologies, present power findings, and explain AI/ML‑based insights to both design and tools teams.
   

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