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ASIC TOP Floorplan Intern, 2027

NVIDIA19 Oct 2026
fulltimeonsite
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Listed location: China, Shanghai

Work arrangement: onsite. A remote label does not confirm worldwide eligibility or visa sponsorship.

Read the employer’s description for qualifications, compensation and work eligibility. Confirm the position is still open on the application page.

Job description supplied by NVIDIA; category and skill labels may be inferred. How our listings work · Report a problem

Job Description

We are now looking for an Intern ASIC TOP Floorplan Design Engineer. NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the world’s leading SoC's and GPU's. This position offers you a unique opportunity to craft and to influence the design and development of the next generation GPU and SoC, allowing you to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.


What you will be doing:

  • Working with architects, design leads, physical design leads and package leads, you will develop and to craft and optimize floorplans during early chip development.
  • Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan improvement opportunities.
  • Solve timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical implementation decisions.
  • You will build tools and improve existing infrastructure to optimize chip area and speed of execution.

What we need to see:

  • Masters Degree in Electrical Engineering, Computer Science, or Computer Engineering or equivalent work/learning experience.
  • Experience in Verilog, System Verilog or similar HVL.
  • Experience with CAD and physical design methodologies (flow and tool development), chip floorplan, power/clock distribution, packaging, P&R and timing closure.
  • Strong communication and interpersonal skills and ability & desire to work as a great teammate should be displayed in your interview.
  • Python, Perl and C/C++ programming language experience.

Ways to stand out from the crowd:

  • Experience in driving development of large scale ASIC floorplan is a huge plus.

NVIDIA is widely considered to be one of the technology world’s most desirable employers. Our products are leading the way with groundbreaking developments in Artificial Intelligence, Autonomous Driving, High-Performance Computing and Visualization. We have some of the most forward-thinking and hardworking people in the world working for us. Are you creative and autonomous? Do you love the challenge of crafting the fastest and most power efficient chips in their class? If so, we want to hear from you.

Skills mentioned

PythonGPU

Frequently asked questions

Is the ASIC TOP Floorplan Intern, 2027 position at NVIDIA remote?

The ASIC TOP Floorplan Intern, 2027 role at NVIDIA does not have a confirmed remote arrangement in our data. Check the employer description for its work location.

What type of employment is the ASIC TOP Floorplan Intern, 2027 role?

NVIDIA is hiring for a full-time ASIC TOP Floorplan Intern, 2027 position.

Which skills are mentioned for the ASIC TOP Floorplan Intern, 2027 job at NVIDIA?

Detected skill labels include Python, GPU. Check the employer description to distinguish required skills from preferred experience.

How do I apply for the ASIC TOP Floorplan Intern, 2027 position at NVIDIA?

You can apply for the ASIC TOP Floorplan Intern, 2027 role directly through NVIDIA's official application link provided on this page.

Interested in this role?

Apply directly on the company's website.

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NVIDIA

NVIDIA

Website
Posted19 Oct 2026
Typefulltime
LevelInternship
LocationChina, Shanghai
Apply NowView All Jobs at NVIDIA

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